1. Technical Field
The present invention relates generally to integrated circuit (IC) design, and more particularly, to IC design providing substantial matching functioning of circuit elements despite use of auto-generated dummy shapes.
2. Related Art
As silicon technologies offer constantly increasing levels of integration, application specific integrated circuit (ASIC) designers are continually challenged to increase productivity and produce larger and larger designs with the same or less resources. Use of smaller circuit elements, sometimes referred to as “macros,” each of which include a predetermined structure for a part of an integrated circuit (IC) and can be used repetitively, is one technique for addressing this challenge. Use of repetitive circuit elements eliminates the need for the IC designer to continually re-design sections of the chip, and therefore improves productivity. As a result, design reuse methodology involving the use of IC circuit elements has become an essential part of IC design.
The designer that uses IC circuit elements is challenged to provide a product that has predictable functioning for these IC circuit elements. One challenge is matching the electrical behavior of two or more instances of the same circuit element in different locations in an IC design. This is generally at odds with automatically generated filler shapes, which are placed in the overall design after the layout is complete, and after the designer has performed all circuit analyses. In particular, if the design system uses automatically placed “dummy fill,” or other auto-generated dummy shapes, the dummy shapes will be automatically placed around the circuit element. If the circuit element is a sensitive circuit, the designer may wish to insure that every instance of the circuit element function matches as identically as possible to every other instance within the IC. Auto-generated dummy shapes, however, are typically located on a consistent grid across an IC design such that different instances of the circuit element may find themselves in substantially different local environments. That is, there is no guarantee that different instances of the same circuit element will see the same local environment, e.g., dummy fill and hole shapes, when placed within the IC design. Any resulting mismatch in electrical parameters (e.g., resistance, capacitance, etc.) is unknown to the designer, and acts to degrade the function of the precision circuits in question. In order to address this issue, many designers attempt to inhibit the automatic generation of dummy shapes in the vicinity of sensitive circuits, and place all required dummy shapes by hand. This approach, however, is more difficult for the designer, and is generally detrimental to the overall manufacturability and process window.
In view of the foregoing, there is a need in the art for a way to design ICs that overcomes the problems of the related art